Field
Embodiments of the present disclosure generally relate to semiconductor devices. More specifically, embodiments described herein relate to horizontal gate all around device structures and methods for forming horizontal gate all around device structures.
Description of the Related Art
As the feature sizes of transistor devices continue to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor device structure to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include a planar structure, a fin field effect transistor (FinFET) structure, and a horizontal gate-all-around (hGAA) structure. The hGAA device structure includes several lattice matched channels suspended in a stacked configuration and connected by source/drain regions.
However, challenges associated with hGAA structures include the existence of a parasitic device at the bottom of the stacked lattice matched channels. Conventional approaches to mitigate the effects of the parasitic device include the implantation of dopants into the parasitic device to suppress leakage of the device. However, a dosage of the dopants required to suppress the leakage may hinder epitaxial growth of device structures on the parasitic device. In addition, implantation may not adequately reduce parasitic capacitance. Another conventional approach utilizes thermal oxidation of a highly doped parasitic device. However, thermal oxidation processes generally require temperatures beyond the thermal budgets of the stacked lattice matched channels.
Accordingly, what is needed in the art are improved methods for forming hGAA device structures.